1. Field of the Invention
The present invention relates to a semiconductor memory and, more particularly, to a semiconductor memory with a built-in parallel bit test mode.
2. Description of the Related Art
Recent dynamic semiconductor memories (DRAMs) have a parallel bit test mode for performing a parallel test of a plurality of bits in order to shorten the test time.
This parallel bit test mode is to access a plurality of bits of a DRAM even with a x1 bit structure, instead of performing writing/reading one bit at a time to test the memory function bit by bit, or to access more bits than the number of inputs/outputs (I/O) for a DRAM with a multi-bit structure, thereby testing the functions of many bits simultaneously. That is, this test mode simultaneously write the same data in n-bit memory cells, simultaneously reads the n-bit data in read mode to determine if each piece of data matches with the written data, and outputs "1" or "0" in accordance with the matched/unmatched result.
This parallel bit test mode can reduce the number of cycles to access all the bits to 1/n (n: the number of bits) and can significantly shorten the test time.
An 8-bit parallel bit test mode that was standardized in JEDEC (Joint Electron Device Engineering Council) has been implemented in a 4M DRAM with a structure of 4M words.times.1 bit to which the parallel bit test mode was introduced first.
As the degree of the integration of DRAMs was increased, the number of bits to be simultaneously tested in parallel bit test mode was also increased to minimize an increase in test time. The individual makers tended to implement a 16-bit parallel mode in 16M DRAMs with a structure of 16M.times.1 bit and implement a 32-bit parallel mode in 64M DRAMs.
While the aforementioned parallel bit test mode will contribute to shortening the test time, the parallel bit width has only been doubled for each generation, so that the time for accessing all the cells has been improved just twice from one generation to a higher one.
In this respect, it is expected that even the parallel bit test mode, which has been considered so far as contributable to shortening the test time, will eventually result in a very long test time for the future generations, thus making an increase in test cost inevitable.
In other words, with regard to semiconductor memories with the conventional parallel bit test mode built therein, as the generation of the memory capacity advances, the test time eventually becomes very long so that the test cost will inevitably increase.